Phase change memory fabricated using self-aligned processing

ABSTRACT

A memory includes transistors in rows and columns providing an array, first conductive lines in columns across the array, and second conductive lines encapsulated by dielectric material in rows across the array. Each second conductive line is coupled to one side of the source-drain path of the transistors in each row. The memory includes phase change elements between the second conductive lines and contacting the first conductive lines and self-aligned to the first conductive lines. Each phase change element is coupled to the other side of the source-drain path of a transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. ______,Attorney Docket Number I331.296.101, entitled “PHASE CHANGE MEMORYFABRICATED USING SELF-ALIGNED PROCESSING” and U.S. patent applicationSer. No. ______, Attorney Docket Number I331.297.101, entitled “PHASECHANGE MEMORY FABRICATED USING SELF-ALIGNED PROCESSING,” both filedconcurrently on the same day with the present application and bothincorporated herein by reference.

BACKGROUND

One type of non-volatile memory is resistive memory. Resistive memoryutilizes the resistance value of a memory element to store one or morebits of data. For example, a memory element programmed to have a highresistance value may represent a logic “1” data bit value, and a memoryelement programmed to have a low resistance value may represent a logic“0” data bit value. The resistance value of the memory element isswitched electrically by applying a voltage pulse or a current pulse tothe memory element. One type of resistive memory is phase change memory.Phase change memory uses a phase change material for the resistivememory element.

Phase change memories are based on phase change materials that exhibitat least two different states. Phase change material may be used inmemory cells to store bits of data. The states of phase change materialmay be referred to as amorphous and crystalline states. The states maybe distinguished because the amorphous state generally exhibits higherresistivity than does the crystalline state. Generally, the amorphousstate involves a more disordered atomic structure, while the crystallinestate involves a more ordered lattice. Some phase change materialsexhibit more than one crystalline state, e.g. a face-centered cubic(FCC) state and a hexagonal closest packing (HCP) state. These twocrystalline states have different resistivities and may be used to storebits of data.

Phase change in the phase change materials may be induced reversibly. Inthis way, the memory may change from the amorphous state to thecrystalline state and from the crystalline state to the amorphous statein response to temperature changes. The temperature changes to the phasechange material may be achieved in a variety of ways. For example, alaser can be directed to the phase change material, current may bedriven through the phase change material, or current can be fed througha resistive heater adjacent the phase change material. In any of thesemethods, controllable heating of the phase change material causescontrollable phase change within the phase change material.

A phase change memory including a memory array having a plurality ofmemory cells that are made of phase change material may be programmed tostore data utilizing the memory states of the phase change material. Oneway to read and write data in such a phase change memory device is tocontrol a current and/or a voltage pulse that is applied to the phasechange material. The level of current and/or voltage generallycorresponds to the temperature induced within the phase change materialin each memory cell.

For data storage applications, reducing the physical memory cell size isa continuing goal. Reducing the physical memory cell size increases thestorage density of the memory and reduces the cost of the memory. Toreduce the physical memory cell size, the memory cell layout should belithography friendly. In addition, since interface resistances betweenmetal and active material within memory cells contributes considerablyto the overall resistance for small areas, the interface areas should bewell controlled. Finally, the memory cell layout should have mechanicalstability to improve the chemical mechanical planarization (CMP) processwindow to enable greater yields.

For these and other reasons, there is a need for the present invention.

SUMMARY

One embodiment of the present invention provides a memory. The memoryincludes transistors in rows and columns providing an array, firstconductive lines in columns across the array, and second conductivelines encapsulated by dielectric material in rows across the array. Eachsecond conductive line is coupled to one side of the source-drain pathof the transistors in each row. The memory includes phase changeelements between the second conductive lines and contacting the firstconductive lines and self-aligned to the first conductive lines. Eachphase change element is coupled to the other side of the source-drainpath of a transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present invention and are incorporated in andconstitute a part of this specification. The drawings illustrate theembodiments of the present invention and together with the descriptionserve to explain the principles of the invention. Other embodiments ofthe present invention and many of the intended advantages of the presentinvention will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 is a diagram illustrating one embodiment of an array of phasechange memory cells.

FIG. 2A illustrates a cross-sectional view of one embodiment of an arrayof phase change memory cells.

FIG. 2B illustrates a perpendicular cross-sectional view of the array ofphase change memory cells illustrated in FIG. 2A.

FIG. 2C illustrates a top view of the array of phase change memory cellsillustrated in FIG. 2A.

FIG. 3A illustrates a cross-sectional view of one embodiment of apreprocessed wafer.

FIG. 3B illustrates a perpendicular cross-sectional view of thepreprocessed wafer illustrated in FIG. 3A.

FIG. 3C illustrates a top view of the preprocessed wafer illustrated inFIG. 3A.

FIG. 4 illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, a conductive material layer, and a first dielectricmaterial layer.

FIG. 4 illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, ground lines, and first dielectric material layerafter etching.

FIG. 6 illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, ground lines, first dielectric material layer, and asecond dielectric material layer.

FIG. 7 illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, ground lines, first dielectric material layer, andsidewall spacers after etching.

FIG. 8A illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, encapsulated ground lines, a phase change materiallayer, and an electrode material layer.

FIG. 8B illustrates a perpendicular cross-sectional view of the waferillustrated in FIG. 8A.

FIG. 9A illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, encapsulated ground lines, phase change materiallayer, and bit lines after etching.

FIG. 9B illustrates a perpendicular cross-sectional view of the waferillustrated in FIG. 9A.

FIG. 9C illustrates a top view of the wafer illustrated in FIG. 9A.

FIG. 10A illustrates a cross-sectional view of one embodiment of apreprocessed wafer.

FIG. 10B illustrates a perpendicular cross-sectional view of thepreprocessed wafer illustrated in FIG. 10A.

FIG. 10C illustrates a top view of the preprocessed wafer illustrated inFIG. 10A.

FIG. 11 illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, a conductive material layer, and a first dielectricmaterial layer.

FIG. 12 illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, ground lines, and first dielectric material layerafter etching.

FIG. 13 illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, ground lines, first dielectric material layer, and asecond dielectric material layer.

FIG. 14 illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, ground lines, first dielectric material layer, andsidewall spacers after etching.

FIG. 15A illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, encapsulated ground lines, and a dielectric materiallayer.

FIG. 15B illustrates a perpendicular cross-sectional view of the waferillustrated in FIG. 15A.

FIG. 16A illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, encapsulated ground lines, dielectric materiallayer, and a phase change material layer.

FIG. 16B illustrates a perpendicular cross-sectional view of the waferillustrated in FIG. 16A.

FIG. 17A illustrates a cross-sectional view of one embodiment of thepreprocessed wafer, encapsulated ground line, phase change materiallayer, and bit lines.

FIG. 17B illustrates a perpendicular cross-sectional view of the waferillustrated in FIG. 17A.

FIG. 17C illustrates a top view of the wafer illustrated in FIG. 17A.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments of the present invention can be positioned ina number of different orientations, the directional terminology is usedfor purposes of illustration and is in no way limiting. It is to beunderstood that other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent invention. The following detailed description, therefore, is notto be taken in a limiting sense, and the scope of the present inventionis defined by the appended claims.

FIG. 1 is a diagram illustrating one embodiment of an array ofphase-change memory cells 100. Memory array 100 is fabricated using linelithography and self-aligned processing to minimize critical lithographysteps. In addition, the interface resistance between metal and activematerial is overlay-insensitive and by maximizing the interface areas,parasitic resistances are minimized. Memory array 100 does not have anyisolated, small patterns such that the chemical mechanical planarization(CMP) process window is improved and mechanical stability is improved.

Memory array 100 includes a plurality of phase-change memory cells 104a-104 d (collectively referred to as phase-change memory cells 104), aplurality of bit lines (BLs) 112 a-112 b (collectively referred to asbit lines 112), a plurality of word lines (WLs) 110 a-110 b(collectively referred to as word lines 110), and a plurality of groundlines (GLs) 114 a-114 b (collectively referred to as ground lines 114).

As used herein, the term “electrically coupled” is not meant to meanthat the elements must be directly coupled together and interveningelements may be provided between the “electrically coupled” elements.

Each phase-change memory cell 104 is electrically coupled to a word line110, a bit line 112, and a ground line 114. For example, phase-changememory cell 104 a is electrically coupled to bit line 112 a, word line110 a, and ground line 114 a, and phase-change memory cell 104 b iselectrically coupled to bit line 112 a, word line 110 b, and ground line114 b. Phase-change memory cell 104 c is electrically coupled to bitline 112 b, word line 110 a, and ground line 114 a, and phase-changememory cell 104 d is electrically coupled to bit line 112 b, word line110 b, and ground line 114 b.

Each phase-change memory cell 104 includes a phase-change element 106and a transistor 108. While transistor 108 is a field-effect transistor(FET) in the illustrated embodiment, in other embodiments, transistor108 can be another suitable device such as a bipolar transistor or a 3Dtransistor structure. Phase-change memory cell 104 a includesphase-change element 106 a and transistor 108 a. One side ofphase-change element 106 a is electrically coupled to bit line 112 a,and the other side of phase-change element 106 a is electrically coupledto one side of the source-drain path of transistor 108 a. The other sideof the source-drain path of transistor 108 a is electrically coupled toground line 114 a. The gate of transistor 108 a is electrically coupledto word line 110 a. Phase-change memory cell 104 b includes phase-changeelement 106 b and transistor 108 b. One side of phase-change element 106b is electrically coupled to bit line 112 a, and the other side ofphase-change element 106 b is electrically coupled to one side of thesource-drain path of transistor 108 b. The other side of thesource-drain path of transistor 108 b is electrically coupled to groundline 114 b. The gate of transistor 108 b is electrically coupled to wordline 110 b.

Phase-change memory cell 104 c includes phase-change element 106 c andtransistor 108 c. One side of phase-change element 106 c is electricallycoupled to bit line 112 b and the other side of phase-change element 106c is electrically coupled to one side of the source-drain path oftransistor 108 c. The other side of the source-drain path of transistor108 c is electrically coupled to ground line 114 a. The gate oftransistor 108 c is electrically coupled to word line 110 a.Phase-change memory cell 104 d includes phase-change element 106 d andtransistor 108 d. One side of phase-change element 106 d is electricallycoupled to bit line 112 b and the other side of phase-change element 106d is electrically coupled to one side of the source-drain path oftransistor 108 d. The other side of the source-drain path of transistor108 d is electrically coupled to ground line 114 b. The gate oftransistor 108 d is electrically coupled to word line 110 b.

In another embodiment, each phase-change element 106 is electricallycoupled to a ground line 114 and each transistor 108 is electricallycoupled to a bit line 112. For example, for phase-change memory cell 104a, one side of phase-change element 106 a is electrically coupled toground line 114 a. The other side of phase-change element 106 a iselectrically coupled to one side of the source-drain path of transistor108 a. The other side of the source-drain path of transistor 108 a iselectrically coupled to bit line 112 a. In general, the ground lines 114have a lower potential than the bit lines 112.

Each phase-change element 106 comprises a phase-change material that maybe made up of a variety of materials in accordance with the presentinvention. Generally, chalcogenide alloys that contain one or moreelements from group VI of the periodic table are useful as suchmaterials. In one embodiment, the phase-change material of phase-changeelement 106 is made up of a chalcogenide compound material, such asGeSbTe, SbTe, GeTe or AgInSbTe. In another embodiment, the phase-changematerial is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb. Inother embodiments, the phase-change material is made up of any suitablematerial including one or more of the elements Ge, Sb, Te, Ga, As, In,Se, and S.

During a set operation of phase-change memory cell 104 a, a set currentor voltage pulse is selectively enabled and sent through bit line 112 ato phase-change element 106 a thereby heating it above it'scrystallization temperature (but usually below it's melting temperature)with word line 110 a selected to activate transistor 108 a. In this way,phase-change element 106 a reaches its crystalline state during this setoperation. During a reset operation of phase-change memory cell 104 a, areset current or voltage pulse is selectively enabled to bit line 112 aand sent to phase-change material element 106 a. The reset current orvoltage quickly heats phase-change element 106 a above its meltingtemperature. After the current or voltage pulse is turned off, thephase-change element 106 a quickly quench cools into the amorphousstate. Phase-change memory cells 104 b-104 d and other phase-changememory cells 104 in memory array 100 are set and reset similarly tophase-change memory cell 104 a using a similar current or voltage pulse.

FIG. 2A illustrates a cross-sectional view of one embodiment of an arrayof phase change memory cells 200. FIG. 2B illustrates a perpendicularcross-sectional view of array of phase change memory cells 200illustrated in FIG. 2A. FIG. 2C illustrates a top view of array of phasechange memory cells 200 illustrated in FIG. 2A. In one embodiment, arrayof phase change memory cells 100 is similar to array of phase changememory cells 200. Array of phase change memory cells 200 includessubstrate 212, transistors 108, word lines 110, first contacts 206,second contacts 208, ground lines 114, dielectric material 210, 216, and230, shallow trench isolation (STI) 214, inter level dielectric (ILD)215, phase change material 107, and bits lines 112. Metal wiring (notshown) follows after the bit line level.

Transistors 108 for selecting storage locations 105 in phase changematerial 107 are formed in substrate 212 in rows and columns. The gatesof transistors 108 are electrically coupled to word lines 110.Dielectric material 210 is deposited over transistors 108 and word lines110. First contacts 206 electrically couple one side of the source-drainpath of each transistor 108 to a ground line 114. Second contacts 208electrically couple the other side of the source-drain path of eachtransistor 108 to a storage location 105, which is a part of phasechange material 107. Each line of phase change material 107 iselectrically coupled to a bit line 112. Bit lines 112 are perpendicularto word lines 110 and ground lines 114. Dielectric material 230insulates ground lines 114 above first contacts 206. Dielectric material216 insulates bits lines 112 and lines of phase change material 107 fromadjacent bit lines 112 and lines of phase change material 107. STI 214insulates transistors 108 from adjacent transistors 108, and ILD 215insulates second contacts 208 from adjacent second contacts 208.

Lines of phase change material 107, which include storage locations 105,are self-aligned to bit lines 112. The self-alignment minimizes criticallithography steps in the fabrication of array of phase change memorycells 200. In addition, with self-alignment the interface resistancesbetween second contacts 208 and phase change material 107 and betweenphase change material 107 and bit lines 112 is overlay insensitive andparasitic resistances are minimized.

In one embodiment, array of phase change memory cells 200 is scalable to8F² for dual gate memory cells, where “F” is the minimum feature size,or to 6F² for single gate memory cells. In the embodiment for singlegate memory cells, an active gate of a transistor 108 between every twoadjacent memory cells is replaced with an isolation gate (i.e., thetransistor is not used as a switch; rather it is always turned off), anda dummy ground line is formed above the isolation gate to separateadjacent memory cells. A first embodiment of a method for fabricatingarray of phase change memory cells 200 is described and illustrated withreference to the following FIGS. 3A-9C. A second embodiment of a methodfor fabricating array of phase change memory cells 200 is described andillustrated with reference to the following FIGS. 10A-17C.

FIG. 3A illustrates a cross-sectional view of one embodiment of apreprocessed wafer 218. FIG. 3B illustrates a perpendicularcross-sectional view of preprocessed wafer 218 illustrated in FIG. 3A.FIG. 3C illustrates a top view of preprocessed wafer 218 illustrated inFIG. 3A. Preprocessed wafer 218 includes substrate 212, transistors 108,word lines 110, first contacts 206, second contacts 208, STI 214, ILD215, and dielectric material 210.

Transistors 108 are formed in substrate 212 in rows and columns. Thegates of transistors 108 are electrically coupled to word lines 110.Dielectric material 210 is deposited over transistors 108 and word lines110. First contacts 206 are electrically coupled to one side of thesource-drain path of each transistor 108. Second contacts 208 areelectrically coupled to the other side of the source-drain path of eachtransistor 108. STI 214 insulates transistors 108 from adjacenttransistors 108, and ILD 215 insulates second contacts 208 from adjacentsecond contacts 208.

First contacts 206 and second contacts 208 are contact plugs, such as Wplugs, Cu plugs, or other suitable conducting material plugs. Word lines110 comprise doped poly-Si, W, TiN, NiSi, CoSi, TiSi, WSi_(X), oranother suitable material. Dielectric material 210 comprises SiN orother suitable material that enables a borderless contact formationprocess for first contacts 206 and second contacts 208. STI 214 and ILD215 comprise SiO₂, fluorinated silica glass (FSG), boro-phosphoroussilicate glass (BPSG), boro-silicate glass (BSG), or other suitabledielectric material. Word lines 110 are perpendicular to STI 214 and ILD215.

FIG. 4 illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, a conductive material layer 114 a, and a firstdielectric material layer 230 a. Conductive material, such as W, Al, Cu,or other suitable conductive material is deposited over preprocessedwafer 218 to provide conductive material layer 114 a. Conductivematerial layer 114 a is deposited using chemical vapor deposition (CVD),atomic layer deposition (ALD), metal organic chemical vapor deposition(MOCVD), plasma vapor deposition (PVD), jet vapor deposition (JVP), orother suitable deposition technique.

Dielectric material, such as SiN or other suitable dielectric material,is deposited over conductive material layer 114 a to provide firstdielectric material layer 230 a. First dielectric material layer 230 ais deposited using CVD, ALD, MOCVD, PVD, JVP, high-density plasma (HDP),or other suitable deposition technique.

FIG. 5 illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114, and first dielectric materiallayer 230 b after etching first dielectric material layer 230 a andconductive material layer 114 a. First dielectric material layer 230 aand conductive material layer 114 a are etched to provide firstdielectric material layer 230 b and ground lines 114 and to formtrenches 220. Line lithography is used to pattern trenches 220 having awidth 221 to expose second contacts 208. The line lithography does notneed to be precisely centered over second contacts 208 as long as secondcontacts 208 are exposed. In this way, the line lithography is lesscritical yet the desired memory cell size is obtained.

FIG. 6 illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114, first dielectric materiallayer 230 b, and a second dielectric material layer 230 c. Dielectricmaterial, such as SiN or other suitable dielectric material, isconformally deposited over exposed portions of first dielectric materiallayer 230 b, ground lines 114, and preprocessed wafer 218 to providesecond dielectric material layer 230 c. Second dielectric material layer230 c is deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or othersuitable deposition technique.

FIG. 7 illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114, first dielectric materiallayer 230 b, and sidewall spacers 230 d after etching second dielectricmaterial layer 230 c. Second dielectric material layer 230 c is etchedusing a spacer etch to form sidewall spacers 230 d and to expose secondcontacts 208. First dielectric material layer 230 b and sidewall spacers230 d are collectively referred to as dielectric material 230.

FIG. 8A illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114 encapsulated by dielectricmaterial 230, a phase change material layer 107 a, and an electrodematerial layer 113 a. FIG. 8B illustrates a perpendicularcross-sectional view of the wafer illustrated in FIG. 8A. Phase changematerial, such as a chalcogenide compound material or other suitablephase change material, is deposited over exposed portions of dielectricmaterial 230 and preprocessed wafer 218 to provide phase change materiallayer 107 a. Phase change material layer 107 a is deposited using CVD,ALD, MOCVD, PVD, JVP, or other suitable deposition technique. In oneembodiment, phase change material layer 107 a is planarized to exposedielectric material 230.

Electrode material, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or othersuitable electrode material, is deposited over phase change materiallayer 107 a to provide electrode material layer 113 a. Electrodematerial layer 113 a is deposited using CVD, ALD, MOCVD, PVD, JVP, orother suitable deposition technique.

FIG. 9A illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114 encapsulated by dielectricmaterial 230, phase change material layer 107, and bit lines 112 afteretching electrode material layer 113 a and phase change material layer107 a. FIG. 9B illustrates a perpendicular cross-sectional view of thewafer illustrated in FIG. 9A, and FIG. 9C illustrates a top view of thewafer illustrated in FIG. 9A. Electrode material layer 113 a and phasechange material layer 107 a are etched to provide bit lines 112 andphase change material layer 107, which is self-aligned to bit lines 112.In the embodiment where phase change material layer 107 a is planarizedto expose dielectric material 230, electrode material layer 113 a andphase change material layer 107 a are etched to provide bit lines 112and phase change elements 106, which are self-aligned to bit lines 112.

In one embodiment, phase change material layer 107 is optionallyundercut etched. Line lithography is used to pattern bit lines 112 andlines of phase change material 107 perpendicular to trenches 220 suchthat each storage location 105 in phase change material 107 contacts asecond contact 208. The line lithography does not need to be preciselycentered over second contacts 208 as long as the bottom portion of eachstorage location 105 in phase change material 107 contacts a secondcontact 208. In this way, the line lithography is less critical yet thedesired memory cell size is obtained.

Dielectric material, such as SiO₂, FSG, BPSG, BSG, or other suitabledielectric material, is deposited over exposed portions of bit lines112, phase change material layer 107, dielectric material layer 230, andpreprocessed wafer 218. The dielectric material layer is deposited usingCVD, ALD, MOCVD, PVD, JVP, HDP, or other suitable deposition technique.The dielectric material layer is planarized to expose bit lines 112 andprovide dielectric material layer 216. The dielectric material layer isplanarized using CMP or another suitable planarization technique toprovide array of phase change memory cells 200 a illustrated in FIGS.2A-2C.

FIG. 10A illustrates a cross-sectional view of one embodiment of apreprocessed wafer 218. FIG. 10B illustrates a perpendicularcross-sectional view of preprocessed wafer 218 illustrated in FIG. 10A.FIG. 10C illustrates a top view of preprocessed wafer 218 illustrated inFIG. 10A. Preprocessed wafer 218 includes substrate 212, transistors108, word lines 110, first contacts 206, second contacts 208, STI 214,ILD 215, and dielectric material 210.

Transistors 108 are formed in substrate 212 in rows and columns. Thegates of transistors 108 are electrically coupled to word lines 110.Dielectric material 210 is deposited over transistors 108 and word lines110. First contacts 206 are electrically coupled to one side of thesource-drain path of each transistor 108. Second contacts 208 areelectrically coupled to the other side of the source-drain path of eachtransistor 108. STI 214 insulates transistors 108 from adjacenttransistors 108, and ILD 215 insulates second contacts 208 from adjacentsecond contacts 208.

First contacts 206 and second contacts 208 are contact plugs, such as Wplugs, Cu plugs, or other suitable conducting material plugs. Word lines110 comprise doped poly-Si, W, TiN, NiSi, CoSi, TiSi, WSi_(X), oranother suitable material. Dielectric material 210 comprises SiN orother suitable material that enables a borderless contact formationprocess for first contacts 206 and second contacts 208. STI 214 and ILD215 comprise SiO₂, FSG, BPSG, BSG, or other suitable dielectricmaterial. Word lines 110 are perpendicular to STI 214 and ILD 215.

FIG. 11 illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, a conductive material layer 114 a, and a firstdielectric material layer 230 a. Conductive material, such as W, Al, Cu,or other suitable conductive material is deposited over preprocessedwafer 218 to provide conductive material layer 114 a. Conductivematerial layer 114 a is deposited using CVD, ALD, MOCVD, PVD, JVP, orother suitable deposition technique.

Dielectric material, such as SiN or other suitable dielectric material,is deposited over conductive material layer 114 a to provide firstdielectric material layer 230 a. First dielectric material layer 230 ais deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or other suitabledeposition technique.

FIG. 12 illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114, and first dielectric materiallayer 230 b after etching first dielectric material layer 230 a andconductive material layer 114 a. First dielectric material layer 230 aand conductive material layer 114 a are etched to provide firstdielectric material layer 230 b and ground lines 114 and to formtrenches 220. Line lithography is used to pattern trenches 220 having awidth 221 to expose second contacts 208. The line lithography does notneed to be precisely centered over second contacts 208 as long as secondcontacts 208 are exposed. In this way, the line lithography is lesscritical yet the desired memory cell size is obtained.

FIG. 13 illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114, first dielectric materiallayer 230 b, and a second dielectric material layer 230 c. Dielectricmaterial, such as SiN or other suitable dielectric material, isconformally deposited over exposed portions of first dielectric materiallayer 230 b, ground lines 114, and preprocessed wafer 218 to providesecond dielectric material layer 230 c. Second dielectric material layer230 c is deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or othersuitable deposition technique.

FIG. 14 illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114, first dielectric materiallayer 230 b, and sidewall spacers 230 d after etching second dielectricmaterial layer 230 c. Second dielectric material layer 230 c is etchedusing a spacer etch to form sidewall spacers 230 d and to expose secondcontacts 208. First dielectric material layer 230 b and sidewall spacers230 d are collectively referred to as dielectric material 230.

FIG. 15A illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114 encapsulated by dielectricmaterial 230, and a dielectric material layer 216 a. FIG. 15Billustrates a perpendicular cross-sectional view of the waferillustrated in FIG. 15A. Dielectric material, such as SiO₂, FSG, BPSG,BSG, or other suitable dielectric material, is deposited over exposedportions of dielectric material 230 and preprocessed wafer 218 toprovide dielectric material layer 216 a. Dielectric material layer 216 ais deposited using CVD, ALD, MOCVD, PVD, JVP, HDP, or other suitabledeposition technique.

FIG. 16A illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114 encapsulated by dielectricmaterial 230, dielectric material layer 216, and a phase change materiallayer 107 a. FIG. 16B illustrates a perpendicular cross-sectional viewof the wafer illustrated in FIG. 16A. Dielectric material layer 216 a isetched to provide dielectric material layer 216. Line lithography isused to pattern trenches perpendicular to trenches 220 such that secondcontacts 208 and portions of dielectric material 230 are exposed. Theline lithography does not need to be precisely centered over secondcontacts 208 as long as second contacts 208 are exposed. In this way,the line lithography is less critical yet the desired memory cell sizeis obtained.

Phase change material, such as a chalcogenide compound material or othersuitable phase change material, is deposited over exposed portions ofdielectric material layer 216, dielectric material 230, and preprocessedwafer 218 to provide a phase change material layer. The phase changematerial layer is deposited using CVD, ALD, MOCVD, PVD, JVP, or othersuitable deposition technique. The phase change material layer isplanarized to expose dielectric material layer 216 to provide phasechange material layer 107 a. The phase change material layer isplanarized using CMP or another suitable planarization technique.

FIG. 17A illustrates a cross-sectional view of one embodiment ofpreprocessed wafer 218, ground lines 114 encapsulated by dielectricmaterial 230, phase change material layer 107, and bit lines 112. FIG.17B illustrates a perpendicular cross-sectional view of the waferillustrated in FIG. 17A, and FIG. 17C illustrates a top view of thewafer illustrated in FIG. 17A. Phase change material layer 107 a isrecess etched to provide phase change material layer 107. Electrodematerial, such as TiN, TaN, W, Al, Cu, TiSiN, TaSiN, or other suitableelectrode material, is deposited over phase change material layer 107and dielectric material layer 216 to provide an electrode materiallayer. The electrode material layer is deposited using CVD, ALD, MOCVD,PVD, JVP, or other suitable deposition technique. The electrode materiallayer is planarized to expose dielectric material layer 216 to providebit lines 112. The electrode material layer is planarized using CMP oranother suitable planarization technique to provide array of phasechange memory cells 200 a illustrated in FIGS. 2A-2C.

Embodiments of the present invention provide an array of phase changememory cells fabricated using line lithography and self-alignedprocessing to minimize critical lithography steps. In addition,interface resistances between metal and active material in the array isoverlay-insensitive and by maximizing the interface areas, parasiticresistances are minimized. The array of phase change memory cells has animproved chemical mechanical planarization (CMP) process window andimproved mechanical stability during fabrication.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

1. A memory comprising: transistors in rows and columns providing anarray; first conductive lines in columns across the array; secondconductive lines encapsulated by dielectric material in rows across thearray, each second conductive line coupled to one side of thesource-drain path of the transistors in each row; and phase changeelements between the second conductive lines and contacting the firstconductive lines and self-aligned to the first conductive lines, eachphase change element coupled to the other side of the source-drain pathof a transistor.
 2. The memory of claim 1, wherein the first conductivelines are bit lines and the second conductive lines are ground lines. 3.The memory of claim 1, further comprising: word lines in rows across thearray, each word line coupled to gates of the transistors in each row.4. The memory of claim 1, wherein the memory is scalable to 6F², where Fis a minimum feature size.
 5. The memory of claim 1, wherein the memoryis scalable to 8F², where F is a minimum feature size.
 6. A memorycomprising: transistors in rows and columns providing an array; firstconductive lines in columns across the array; second conductive linesencapsulated by dielectric material in rows across the array, eachsecond conductive line coupled to one side of the source-drain path ofthe transistors in each row; and phase change material in columns acrossthe array and providing storage locations between the second conductivelines, the phase change material contacting the first conductive linesand self-aligned to the first conductive lines, each storage locationcoupled to the other side of the source-drain path of a transistor. 7.The memory of claim 6, wherein the first conductive lines are bit linesand the second conductive lines are ground lines.
 8. The memory of claim6, further comprising: word lines in rows across the array, each wordline coupled to gates of the transistors in each row.
 9. The memory ofclaim 6, wherein the memory is scalable to 6F², where F is a minimumfeature size.
 10. The memory of claim 6, wherein the memory is scalableto 8F², where F is a minimum feature size.
 11. A method for fabricatinga memory, the method comprising: providing a preprocessed waferincluding first contacts and second contacts; fabricating firstconductive lines encapsulated with a dielectric material on thepreprocessed wafer, the first conductive lines contacting the firstcontacts; depositing a phase change material layer over exposed portionsof the dielectric material and the preprocessed wafer; depositing anelectrode material layer over the phase change material layer; andetching the electrode material layer and the phase change material layerto form second conductive lines and phase change material self-alignedto the second conductive lines, the phase change material providingstorage locations contacting the second contacts.
 12. The method ofclaim 11, wherein fabricating the first conductive lines encapsulatedwith the dielectric material comprises: depositing a conductive materiallayer over the preprocessed wafer; depositing a first dielectricmaterial layer over the conductive material layer; etching the firstdielectric material layer and the conductive material layer to formtrenches exposing the second contacts and to provide first conductivelines contacting the first contacts; conformally depositing a seconddielectric material layer over exposed portions of the first dielectricmaterial layer and the first conductive lines; and etching the seconddielectric material layer to provide sidewall spacers such that thefirst conductive lines are encapsulated by the first dielectric materiallayer and the sidewall spacers.
 13. The method of claim 11, whereinfabricating the first conductive lines comprises fabricating groundlines.
 14. The method of claim 11, wherein etching the electrodematerial layer to form the second conductive lines comprises etching theelectrode material layer to form bit lines.
 15. A method for fabricatinga memory, the method comprising: providing a preprocessed waferincluding first contacts and second contacts; fabricating firstconductive lines encapsulated with a dielectric material on thepreprocessed wafer, the first conductive lines contacting the firstcontacts; depositing a phase change material layer over exposed portionsof the dielectric material and the preprocessed wafer; planarizing thephase change material layer to expose the dielectric material;depositing an electrode material layer over the phase change materiallayer and the dielectric material; and etching the electrode materiallayer and the phase change material layer to form second conductivelines and phase change elements self-aligned to the second conductivelines, each phase change element contacting a second contact.
 16. Themethod of claim 15, wherein fabricating the first conductive linesencapsulated with the dielectric material comprises: depositing aconductive material layer over the preprocessed wafer; depositing afirst dielectric material layer over the conductive material layer;etching the first dielectric material layer and the conductive materiallayer to form trenches exposing the second contacts and to provide firstconductive lines contacting the first contacts; conformally depositing asecond dielectric material layer over exposed portions of the firstdielectric material layer and the first conductive lines; and etchingthe second dielectric material layer to provide sidewall spacers suchthat the first conductive lines are encapsulated by the first dielectricmaterial layer and the sidewall spacers.
 17. The method of claim 15,wherein fabricating the first conductive lines comprises fabricatingground lines.
 18. The method of claim 15, wherein etching the electrodematerial layer to form second conductive lines comprises etching theelectrode material layer to form bit lines.
 19. A method for fabricatinga memory, the method comprising: providing a preprocessed waferincluding first contacts and second contacts; fabricating firstconductive lines encapsulated with a first dielectric material on thepreprocessed wafer, the first conductive lines contacting the firstcontacts; depositing a second dielectric material layer over exposedportions of the first dielectric material and the preprocessed wafer;etching trenches in the second dielectric material layer to expose thesecond contacts and portions of the first dielectric material;depositing phase change material over exposed portions of the seconddielectric material layer, the first dielectric material, and thepreprocessed wafer; planarizing the phase change material layer toexpose the second dielectric material layer; recess etching the phasechange material layer; depositing an electrode material layer overexposed portions of the second dielectric material layer and the phasechange material layer; and planarizing the electrode material layer toexpose the second dielectric material layer to form second conductivelines self-aligned to the phase change material, the phase changematerial providing storage locations contacting the second contacts. 20.The method of claim 19, wherein fabricating the first conductive linesencapsulated with the first dielectric material comprises: depositing aconductive material layer over the preprocessed wafer; depositing athird dielectric material layer over the conductive material layer;etching the third dielectric material layer and the conductive materiallayer to form trenches exposing the second contacts and to provide firstconductive lines contacting the first contacts; conformally depositing afourth dielectric material layer over exposed portions of the thirddielectric material layer and the first conductive lines; and etchingthe fourth dielectric material layer to provide sidewall spacers suchthat the first conductive lines are encapsulated by the third dielectricmaterial layer and the sidewall spacers.
 21. The method of claim 19,wherein fabricating the first conductive lines comprises fabricatingground lines.
 22. The method of claim 19, wherein planarizing theelectrode material layer to form the second conductive lines comprisesplanarizing the electrode material layer to form bit lines.